A variety of Texas Instruments digital media processors have been developed for digital cameras and the digital media players. These processors are designed for products requiring high data transfer throughput including portable media players (PMP).
One of the major functions of PMP is to play movies requiring mass storage in hard drives of extremely small physical size. The movie playback frame rate and resolution both depend on a high level of data transfer throughput between the PMP and the hard drive it accesses.
Digital movie data in portable media players is generally compressed in an MPEG4 format and utilizes mass storage in the range of many gigabytes. The movie playback frame rate and resolution depend on how effectively the processor can respond to data coming from the hard drive. Playback quality is a direct function of the level of throughput that the PMP player and its storage medium can offer.
Integrated Drive Electronics (IDE) was created as a way to standardize the use of hard drives in computers with the hard drive and the controller combined. The controller is a small circuit board with semiconductor chips that guide how the hard drive stores and accesses data. Most controllers also include some memory that acts as a buffer to enhance hard drive performance.
Before IDE, controllers and hard drives were separate and often proprietary. Thus, a controller from one manufacturer might not operate properly with a hard drive from another manufacturer. The distance between the controller and the hard drive could result in poor signal quality and affect performance. IBM introduced the AT computer in 1984 with a several key innovations.
1. Additional slots in the computer for adding cards used a new version of the Industry Standard Architecture (ISA) bus. The new bus was capable of transmitting information 16 bits at a time, compared to 8 bits on the original ISA bus.
2. A hard drive designed for the AT computer was introduced using a new combined drive/controller. A ribbon cable from the drive/controller combination ran to an ISA card to connect to the computer, giving birth to the AT Attachment (ATA) interface.
3. In 1986 ATA standard drives were introduced. This drive/controller combination was based on the ATA standard developed by IBM. Vendors then began offering IDE drives. IDE became the term that covered the entire range of integrated drive/controller devices. Since almost all IDE drives are ATA-based, the two terms are used interchangeably.
Currently, an IDE hard disk may be configured to work in one of the five programmable I/O modes with a range of corresponding data transfer rates. Table 1 summarizes the mode designations of the five currently identified programmable I/O modes and their transfer rates.
TABLE 1Data RateAccess RatePIO Mode(Mbytes/sec)(nsec/access)PIO-03.3606PIO-15.2385PIO-28.3240PIO-311.1180PIO-416.6120The host digital media processor negotiates the desired data transfer rate with the IDE hard disk during initialization depending on the capability of the hard disk. Older hard disk drives may accommodate only one of the lower programmable I/O modes, but many newer hard disks can support all the transfer rates of Table 1. Likewise slower processors cannot access hard disks at the higher programmable I/O modes.
FIG. 1 illustrates a block diagram of a host digital media processor (DMP) 100 and its interface in Prior Art to an ATA/IDE high-density drive media device 101 via a CFC True IDE Mode interface 102 built into the digital media processor 100. The ATA-IDE HDD controller 103 is shown separately to emphasize the presence of I/O registers crucial to HDD operation. Compact Flash Association specification rev. 1.4 dated 1998 defines the compact flash card (CFC), which allows for three major modes of usage: PC Card Memory Mode; PC Card I/O Mode; and CFC True IDE Mode.
The CFC True IDE Mode interface 102 built in to the digital media processor chip supports CFC card data transfers where each read or write access to the hard disk takes typically 255 nsec per word (slower than the programmable I/O-2 mode). Thus the use of the CFC True IDE interface requires that the digital media processor must set the hard disk to work at programmable I/O-1 mode rate where maximum throughput is 5.2 Mbytes per second. In CFC True IDE Mode, CFC True IDE interface 102 uses signals 104 derived from the DMP processor to drive the ATA/IDE HDD high density drive 101. Table 2 lists the signals for read cycle timing.
TABLE 2MinMaxItemSymbolnsecnsecData delay after IORD_ (212)tDdRD—100Data hold followingtDhRD0IORD_ (211)IORD_ width (208)twRD165Address setup beforetAsuRD70IORD_ (205)Address hold after IORD_ (206)tAhRD20CE_ setup before IORD_ (207)tCEsuRD5CE_ hold followingtCEhRD20IORD_ (209)
FIG. 2 illustrates descriptive waveforms of the read signals. These read signals include:
ADDR_valid (201) defines the time window for which addressing is valid;
CE_ 202 is a chip enable signal for read operations and is active low;
IORD_ 203 determines duration of READ cycle and is active low;
Data[15:0] 204 defines data read interval;
tAsuRD 205 is the address setup time prior to IORD_;
tAhRD 206 is the address hold after IORD_;
tCEsuRD 207 is the chip enable setup time prior to leading edge of IORD_;
twRD 208 is the pulse width of IORD_;
tCEhRD 209 is the chip enable hold time after trailing edge of IORD_;
tDsuRD 210 is the data setup time prior to trailing edge of IORD_;
tDhRD 211 is the data hold time after trailing edge of IORD_; and
tDdRD 212 is the data delay time after leading edge of IORD_.
Table 3 lists the signals for write cycle timing.
TABLE 3MinMaxItemSymbolnsecnsecData delay after IOWR_ (312)tDdWR—60Data hold followingtDhWR30IOWR_ (311)IOWR_ width (308)twWR165Address setup beforetAsuWR70IOWR_ (305)Address hold after IOWR_ (306)tAhWR20CE_ setup before IOWR_ (307)tCEsuWR5CE_ hold followingtCEhWR20IOWR_ (309)
FIG. 3 illustrates descriptive waveforms of the write signals. These write signals include:
ADDR_valid 301 defines the time window for which addressing is valid;
CE_ 302 is the chip enable signal for write operations and is active low;
IOWR_ 303 determines the duration of a WRITE cycle and is active low;
Data[15:0] 304 defines the data write interval;
tAsuWR 305 is the address setup time prior to IOWR_;
tAhWR 306 is the address hold after IOWR_;
tCEsuWR 307 is the chip enable setup time prior to leading edge of IOWR_;
twWR 308 is the pulse width of IOWR_;
tCEhWR 309 is the chip enable hold time after trailing edge of IOWR_;
tDsuWR 310 is the data setup time prior to trailing edge of IOWR_;
tDsuWR 311 is the data hold time after trailing edge of IOWR_; and
tDdWR 312 is the data delay time after leading edge of IOWR_.
FIG. 4 illustrates the ATA/IDE HDD controller 103 and associated registers 105 for extended memory interface (EMIF) addressing and control signals to the HDD I/O registers 105 of the prior art. Two types of data are involved in the HDD operation: (a) control data to direct operation from the HDD registers 105; and (b) information data to be stored. In initial operation of any read/write cycle, control data is transferred from the host to the HDD controller addressable registers 401 through 410. Then the ATA/IDE HDD controller 103 performs all of the operations necessary to properly write information data to, or read information data from the media. Information data 430 read from media device 101 is stored in device buffer 407 pending transfer to cache 106. In the write cycle, information data 430 is transferred from cache 106 to device buffer 407 to be written to media 101. ATA/IDE HDD controllers 103 using this interface are programmed by the host computer to perform commands and return status to the host at command completion.
Communication to or from HDD media device 101 is through host interface 400 to I/O registers 401 through 410 that route the input or output data to or from registers addressed by the signals from the host:                (CSO_, CS1_, DA[2:0], DIOR_, and DIOW_)All data written to any of the registers 401 through 410 pass from the host via input 430. Inputs 431 through 433 provide all the control signals described in conjunction with FIGS. 2 and 3.        
Control block registers driven by HDD device control 421 and HDD data control 422 are used for device control and to post alternate status. These registers include: write control register 401; alternate status registers 402; and data register 407.
Command block registers are used for sending commands to the device or posting status from the device. These registers include: write command register 403; read status register 404; cylinder high register 405; cylinder low register 406; device/head register 409; error register 412; features register 413; sector count register 410; and sector number register 408.